1. Field of the Invention
The present invention relates to a cache memory, and more particularly to a cache memory, in which a word-line voltage control logic unit and a word-line driver are added as a logic circuit between a row decoder and a word line, so that a reinforcement voltage signal having a higher level than a basic voltage signal can be applied when accessing the word line corresponding to an access time failure, thereby decreasing an access time delay in the word line in order to minimize an access failure to the cache memory due to process variation.
2. Description of the Related Art
With development of semiconductor technologies, nano-scale technologies have been applied to a chip fabrication. As the size of a transistor used in a chip becomes smaller, a problem of process variation has been on the rise. As a problem that did not occur in a conventional large-scale chip, there is a little difference in characteristics (e.g., the length of an effective channel, the thickness of an oxide layer, etc.) among fabricated transistors.
Accordingly, in the case of a 6-transistors static random-access memory (6T SRAM) cell generally used in a cache memory, if six transistors are a little different in characteristics, two problems may arise. Specifically, it may be unpunctual in an access time and unable to read/write.
Such problems may cause the whole of a cache line having a defect to be unable, and bring a system failure in the case of a direct-mapped cache. In even the case of a set-associative cache, it is impossible to use all ways, thereby causing damage in performance.
In result, there is an unusable cache line owing to the foregoing defect, and thus a yield of the cache memory decreases. Particularly, an access failure due to the unpunctual access time is far more likely to occur than unstable reading/writing. In the case of an L1 cache, because the access has to be accomplished within one cycle, it is very important to consider the access failure in designing the access.